Anyone else have something that is kind of obvious finally make sense, and it probably shouldn’t have taken you so long?
Here’s my “guy on the slow boat” discovery of the day:
Why (or at least part of why) are so many DAC chips spec’d at 32-bit 768kHz PCM and DSD512? It finally struck me today: at these two settings, both PCM and DSD are the same data rate! And that data rate is correlated to a very specific clock frequency.
First the data rate:
PCM: 705.6kHz * 32-bit * 2 channels = 45.1584 Mb / s
DSD: 22.5792MHz * 1-bit * 2 channels = 45.1584 Mb / s
Does 45.1584 look familiar? It should, it’s one of two common clock frequencies used in DAC design:
45.158MHz and 49.152MHz!
It turns out the 49.152MHz clock corresponds to 48kHz based source material:
PCM: 768kHz * 32-bit * 2 channels = 49.152 Mb / s
DSD: 24.576MHz * 1-bit * 2 channels = 49.152 Mb / s
With these commonly used precision clock sources in a DAC the system can capture and process the input data stream at this frequency (and at multiples of two below) without having to use a PLL to synthesize the clock frequencies. Just basic divide-by-2, divide-by-4, divide-by-8, and divide-by-16 covers it. (Literally 4 flip-flops, with some overhead logic to make sure the system doesn’t barf.) Doing it this way makes the design very straight forward.
My god! The engineers were paying attention when the architected this system!
Something much less obvious, but kind of cool for anyone interested in some very nerdy clock design information:
Phase noise (the thing that integrates to create jitter) is reduced by dividing the clock frequency down. Specifically it reduces by 10 x log10 (divide_value). So for base frequency data coming into a DAC (ie 44.1kHz or 48kHz), the clock that is capturing and processing the data gets the benefit of reducing whatever noise the main oscillator has while running at 45.158MHz and 49.152MHz divided by 10*log(16) = ~12. So 1/12 the noise of the oscillator (assuming other noise sources aren’t already holding the noise floor above this). So there is some theoretical benefit here to running a lower data rate into a DAC. But often this performance gain is more than overcome by not having to upconvert the data later. So probably still better to pass in higher PCM data rate files in the first place.
